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NXP Semiconductors Application note

Document Number: AN5283 Rev. 1.0, 4/2016

VR5100 layout guidelines

Introduction

This document covers best practices for the layout of the VR5100 device on printed circuit boards. The VR5100 is a SMARTMOS Power Management Integrated Circuit (PMIC) designed specifically for use with the NXP LS1 family of communications processors.

Packaging

The VR5100 device supports consumer and industrial applications and is offered in a standard 48 QFN with an area of 7.0 mm x 7.0 mm. Refer to Table 1. for the package drawing information for both packages. Refer to Application Note AN1902 for guidelines on the handling and assembly of NXP QFN packages during PCB assembly. AN1902 also provides guidelines for PCB design and rework, and package performance information (such as Moisture Sensitivity Level (MSL) rating, board level reliability, mechanical and thermal resistance data). Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and search for the drawing number. Table 1. Package drawing information Package

Suffix

Package outline drawing number

48-pin QFN 7X7 mm - 0.5mm pitch

98ASA00719D

Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 3 Recommended layer stack . . . . . . . . . . . . . . . . . . . .2 4 Component placement hints . . . . . . . . . . . . . . . . . . .2 5 General routing guidelines . . . . . . . . . . . . . . . . . . . .3 6 I2C communication signals . . . . . . . . . . . . . . . . . . . .3 7 Switching power supply traces . . . . . . . . . . . . . . . . .4 8 Effective grounding . . . . . . . . . . . . . . . . . . . . . . . . . .7 9 Exposed pad connection . . . . . . . . . . . . . . . . . . . . . .8 10 Feedback signals . . . . . . . . . . . . . . . . . . . . . . . . . . .8 11 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Recommended layer stack

Table 2. and Table 3. shows the recommended layer stack-up for effective signal shielding. Table 2. Four layer stack-up recommendation Layer

Stack-up

Layer 1 (Top)

High di/dt nodes

Layer 2 (Inner 1)

GND

Layer 3 (Inner 2)

Small signal/Power

Layer 4 (Bottom)

Small signal/GND

Table 3. Six layer stack-up recommendation Layer

Stack-up

Layer 1 (Top)

High di/dt nodes

Layer 2 (Inner 1)

GND

Layer 3 (Inner 2)

Small signal/Power

Layer 4 (Inner 3)

Small signal/Power

Layer 5 (Inner 4)

GND

Layer 6 (Bottom)

High di/dt nodes

Place the ground layer between the high di/dt nodes layer and the sensitive small signal trace layer. The ground layer then shields the small signal traces from switching traces and improves the stability and accuracy of the regulation. Note: A more detailed layer design may be required to route the LS1 processor. If the VR5100 is affected by interference from an LS1 processor, just four of the layers are needed to route it.

Component placement hints

Place these components as close as possible to the IC in order of priority: 1.

Input capacitor of the buck regulators (SW1, SW2, and SW3)

Output diode and output capacitor of the boost converter (SWBST)

VIN, VGB, VCC, VDIG capacitors

LICELL capacitor (if a coin cell is used in system)

VSNVS, REFOUT and linear regulators capacitors (LDOx, VSD and V33)

Switching regulator inductors

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General routing guidelines

General routing guidelines • • • • • •

Shield regulator feedback paths from noise planes and traces and connect them as close as possible to the load (i.e. SW1FB.) The exposed pad (EP) on the VR5100 is the high-current ground return for all the buck regulators and the boost regulator. Use vias under the EP to drop onto the ground plane(s) directly, ensuring sufficient copper for the ground return. The SWxIN, SWxLX, and SWBSTLX nodes are high dI/dt nodes and act as antennas. They are also high current paths. Hence their traces must be kept short and wide. Avoid coupling traces between sensitive signal/low noise supplies (like VBG) and switching nodes. Power components should all be placed on the same side of board and their power traces routed on the same layer in order to reduce voltage drop. If it is necessary to route a power trace to another layer, choose a trace in low di/dt paths (see Figure 2 and Figure 5) and use multiple vias for interconnection. - To minimize noise propagation and connection impedance between layers.

Minimize and isolate/shield the high dv/dt SW node areas. - To minimize the EMI noise source from the high dv/dt SW nodes Separate input current paths among supplies if there is more than one supply on the same input rail (Figure 8) and the supplies are not synchronized. To avoid common impedance noise coupling among supplies, use a local input decoupling capacitor for each supply.

I2C communication signals

To prevent I2C communication signals from being contaminated by nearby high power or high frequency signals, shield I2C signals with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the length of the signal trace.

Figure 1. Recommended shielding for critical signals

VR5100 layout guidelines, Rev. 1.0 NXP Semiconductors 3

Switching power supply traces

In the buck and boost configurations, the length of the 'critical traces' must be minimized. 'Critical traces' refers to current paths having high dI/dt. Refer to Section 7.1 "Buck regulator" and Section 7.2 "Boost converter" for details.

7.1

Buck regulator

Figure 2 shows current paths in a buck converter in the 'on' and 'off' periods of the switching cycle. Critical traces refer to traces that either conduct only during the 'on' periods or only during the 'off' periods, as highlighted in red.

Control FET On

Synchronous FET On

SWxIN

SWxLX

Critical Traces

Figure 2. Buck converter critical traces The top and bottom MOSFETs are integrated within the package in the VR5100 buck regulators. Placing the input capacitor close to the SWxIN pin and the exposed pad (EP) is critical. Figure 4 and show an example layout for the buck regulators.

VR5100 layout guidelines, Rev. 1.0 4

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Switching power supply traces

Figure 3. SW1 schematic – reference for Figure 4

C18 SW1LX C16 Multilayer chip inductor C13

Figure 4. SW1 layout – top layer components and top silkscreen

VR5100 layout guidelines, Rev. 1.0 NXP Semiconductors 5

Switching power supply traces

7.2

Boost converter

Figure 5 shows the critical traces in a boost converter.

Control FET On

Diode conducting

SWBSTLX

Critical traces EP

Figure 5. Boost converter critical traces The switching MOSFET is integrated within the package in the VR5100’s SWBST regulator. The loop formed by the switching MOSFET, the diode and the output capacitor must be minimized to keep parasitic inductances small. Figure 7 and Figure 8 show an example of the SWBST layout.

Figure 6. SWBST schematic – reference for Figure 7 and Figure 8

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Effective grounding

Figure 7. SWBST example layout. Top layer components and top silkscreen

Figure 8. SWBST example layout. Bottom layer components and top and bottom silkscreen Notice that the critical traces (blue and yellow) are kept wide and short on the previous layout example. The return current path is reduced by populating C16 on the bottom and with its negative terminal close to the EP ground plane. A sufficient number of vias is used when changing the high current path from top to bottom layer.

Effective grounding • • •

The practice of 'star grounding' must be followed to achieve optimal performance with the VR5100. The exposed pad (EP) is the ground return for all the switching regulators and should be connected to the ground plane through multiple vias. SGND, SGND1 and SGND2 are signal ground pins and should be connected together though ground plane using separate vias, not through EP. This prevents coupling from return currents of the switching regulators using the EP as a return path. Ground return currents from the switching regulators must not flow through these pins.

VR5100 layout guidelines, Rev. 1.0 NXP Semiconductors 7

Exposed pad connection

The exposed pad (EP) is the ground return for all the switching regulators and should be connected to the ground plane(s) through vias. A minimum of 16 vias is recommended under the EP. The EP also acts as a heat sink for the VR5100, so the vias should not have thermal relief. To reduce unnecessary thermal stress, allow sufficient copper area for the EP. An efficient way to achieve this is to duplicate the EP ground plane on all layers. When routing high current paths, a sufficient number of vias should be placed in parallel to help reduce the parasitic impedance. The vias must be solid thermal vias as shown in Figure 9.

Thermal Relief Via - Not Recommended

Solid Thermal Via - Recommended

Figure 9. Types of via 'Wicking' of solder through the bore in the vias increases their thermal resistance. Follow techniques such as tenting or via encroaching to prevent solder wicking. Using a bore diameter of 0.3 mm or less also helps minimize wicking due to the surface tension of the liquid solder. Apply the solder paste to approximately 50% to 75% of the area of the exposed pad. Rather than applying the solder paste in one large section, apply it in multiple smaller sections. This can be accomplished by using an array of openings in the solder stencil. Sectioning results in a more even spreading of the solder. It also minimizes out-gassing, which can create voids and bridges under the exposed pad. Figure 10 shows an example of how the exposed pad might be laid out.

Figure 10. Exposed pad via array

Feedback signals

The control loop regulates output voltage at the point where the feedback trace meets the output rail. Connect the feedback trace to the output voltage rail near the load for best load regulation. Ensure this trace does not couple noise from other traces/layers. An efficient way to route the feedback trace is to place it alongside the output trace.

VR5100 layout guidelines, Rev. 1.0 8

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References

NXP.com Support Pages

Description

URL

VR5100

Product Summary Page

www.nxp.com/VR5100

AN1902

QFN Application Note

www.nxp.com/files/analog/doc/app_note/AN1902.pdf

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Revision history

Revision 1.0

Date 4/2016

Description of changes •

Initial release

VR5100 layout guidelines, Rev. 1.0 10

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Document Number: AN5283 Rev. 1.0 4/2016